Capture circuits measure the time between edges of an input signal. Capture circuits have many uses. Capture circuits can measure signal frequency. A Hall effect sensor on a motor generates a pulse when a magnetic field crosses the sensor. The frequency of these pulses is directly proportional to the rotating speed of the motor.
FIG. 1 illustrates a prior art method using capture circuits to measure frequency. The capture circuit detects time of the signal transition from low to high at time t1 (101). The input signal returns to low at a variable time t2 from 102 to 103. The capture circuit detects the time of the next signal transition similar to the initial signal transition at time t3 (104). As shown in FIG. 1 the frequency f of the input signal is 1/(t3−t1).
Capture circuits can measure the propagation time of signals. A transmitter generates an ultrasonic signal pulse. The pulse reflects off a distant object and the returning pulse is then received at the source. The pulse time delay from transmission to reception is proportional to the distance traveled by the pulse. Capture circuits can measure the phase shift of signals. The input current of an AC load is measured. Using the input voltage as a reference, a zero crossing circuit generates a pulse which is proportional to the phase difference between the voltage and the current. This pulse duration is proportional to the phase difference. This measured phase difference can be used for power factor correction.
Capture circuits can measure the duty cycle of signals. A circuit generates an output pulse train having a fixed frequency. The high and low pulse widths are proportional to the input voltage to the circuit. Measuring the duration of the high and low pulse enables the signal to be converted back to a digital representation. This method can perform analog to digital conversion.
FIG. 2 illustrates a prior art method measuring duty cycle. The capture circuit detects time of the signal transition from low to high at time t1 (201). The input signal returns to low at a variable time t2 from 202 to 203. The capture circuit detects the time of the next signal transition similar to the initial signal transition at time t3 (104). As shown in FIG. 2 the length of the high signal th is t2−t1 and the length of the low signal t1 is t3−t2. The time of one complete cycle T is t3−t1. Thus the high signal duty cycle is th/T or (t2−t1)/(t3−t1). The low signal duty cycle is t1/T of (t3−t2)/(t3−t1).
Existing capture circuits sample an input signal at a sample frequency. This sample frequency is generally a known constant frequency. The capture circuit synchronizes the input signal to the sampling frequency. This synchronization may introduce one to two cycles of sampling delay. The capture circuit then time stamps the input signal edges.
Time stamping is generally performed using a counter incremented at input signal sample rate. Upon detection of an input signal edge, the current counter value is then latched into a register. Upon detection of the next edge transition, the counter value is captured again. Many applications use a new capture register so that multiple time stamp edges can be buffered.
FIG. 3 is a simplified block diagram of a prior art capture circuit 300. Input signal 301 and sample clock 302 having a frequency fs are supplied to synchronization circuit 311. The resultant synchronized signal 303 supplies one input of edge detector 312. Edge detector 312 also receives sample clock 302. Edge detector 312 generates a capture signal upon detection of predetermined edge in the synchronized signal. Free running multibit counter 313 counts at the frequency of sample clock 302. A selected one of registers 321 to 329 captures and stores the plural bit state of free running counter 313 upon receipt of the capture signal from edge detector 312. The value of data stored within registers 321 to 329 enables the various measurements possible with the capture circuit. The data stored within registers 321 to 329 is readable for use in other parts of an electronic system including capture circuit 300 via data output 350.
FIG. 4 illustrates the operation of synchronization circuit 311. Input signal 301 has a transition from low to high at time 401. Operation of synchronization circuit 311 delays the corresponding low to high transition in synchronized signal 303 until time 402 coincident with a low to high transition in sample clock 302. Input signal 301 has a transition from high to low at time 403. Operation of synchronization circuit 311 delays the corresponding high to low transition in synchronized signal 303 until time 404 coincident with a high to low transition in sample clock 302.
The resolution of the capture circuit depends upon sampling techniques and is limited to the sampling frequency. If fs=100 MHz, then the sampling resolution Tsr= 1/100 MHz=10.0 nSec. To improve the sampling resolution Tsr, one must increase the sampling frequency fs. To achieve a sampling resolution of 1.0 nSec, requires a sampling frequency fs=1 GHz. To achieve a sampling resolution Tsr of 0.5 nSec, requires a sampling frequency fs=2 GHz.
Achieving such high sampling frequencies is not practical or achievable in many integrated circuit technology nodes or requires special design techniques. In many designs there is a need to have many individual capture circuits and this further limits the maximum usable frequencies. Most low cost embedded processors have frequencies be in the order of 40 MHz to 100 MHz. This limits the practical resolution of such systems to around 25 nSec to 10 nSec.